Latest posts and insights
Wheels turning sideways in the water, an automatic gearbox shifting wrong in sand, triggers on the wrong time base, an autopilot driving through pedestrians.
How Project Chrono sits inside Unreal Engine 5.8 as a physics core: modules, classes, per-frame data flow, coordinates, fixed time step, terrain and own forces.
Why a multibody library instead of game physics, what the island demo actually computes, and how an engineer with an agent got there in two days.
The dsPIC33CH carries two DSC cores on one chip, hard-wired as master and slave, with mailbox registers in hardware instead of shared memory. Why that removes the cache coherence pitfall along the way, and where the safety hardware for IEC 60730 Class B, ASIL-B and ASIL-C really pays off.
The STM32H7 dual-core family carries a Cortex-M7 and a Cortex-M4 on one chip. How to set up a separate FreeRTOS on each core and couple them with a FreeRTOS message buffer in the shared, non-cacheable SRAM4, woken up by the hardware semaphore.
The analog front end sets the noise floor of a DSP system. Seven real-world pitfalls that ruin the signal-to-noise ratio before the algorithm even starts: DC/DC ripple, LDO PSRR, anti-aliasing, grounding, bus protection and layout.
